Low power memory device

ABSTRACT

A memory device includes a memory cell unit, a bit line unit and a buffering unit. The memory cell unit includes a plurality of memory cell groups. Each memory cell group includes at least one memory cell for storing data therein. The bit line unit includes a plurality of first bit lines each coupled to the at least one memory cell of a respective memory cell group, and a second bit line for transmitting to-be-read data. The buffering unit includes a plurality of two-state buffers. Each two-state buffer has an input terminal coupled to a respective first bit line, and an output terminal coupled to the second bit line. The memory device does not require a sense amplifier, and thus consumes relatively small power. The memory device can operate at a relatively high frequency when properly configured.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the priority of Taiwanese Application No.103111756, filed on 28 Mar. 2014, the disclosure of which is herebyincorporated by reference.

TECHNICAL FIELD

This invention relates to a memory device, and more particularly to alow power memory device.

BACKGROUND

Referring to FIG. 1, a conventional memory device includes a memory cellarray 10, a plurality of parallel bit lines 11 coupled to the memorycell array 10, and a plurality of parallel word lines 12 coupled to thememory cell array 10.

The memory cell array 10 includes a plurality of memory cells 13. Theword lines 12 intersect the bit lines 11, and are electrically isolatedfrom the bit lines 11. The word lines 12 transmit a control input to thememory cells 13 in order to control the memory cells 13 to output datastored therein to the bit lines 11.

As the demand for storage capacity of memory devices increases, memorycell arrays 10 with many more memory cells 13 would be preferable.However, to accommodate this, each bit line 11 is made longer to becoupled to more memory cells 13, which inevitably increases acapacitance seen thereat.

Because of the relatively large capacitance seen at each bit line 11,voltages outputted by the memory cells 13 may not promptly propagate tothe bit lines 11 (i.e., the memory cells 13 may not be able to drive thebit lines 11 efficiently). As a result, a plurality of sense amplifiers14 are employed to be coupled respectively to the bit lines 11 to assistin amplifying voltages on the bit lines 11 in order to facilitate datatransmission and allow the memory device to operate at a higherfrequency.

Nonetheless, the sense amplifiers 14 may be undesirable components ofthe memory device due to their relatively large power consumption.Therefore, it may be beneficial to attempt to address the issue of thecapacitance seen at each bit line 11, and to omit the sense amplifiers14 altogether.

SUMMARY

Therefore, an object of this invention is to provide a memory devicethat does not require a sense amplifier, and that consumes relativelysmall power.

According to one aspect of this invention, a memory device comprises amemory cell unit, a bit line unit and a buffering unit. The memory cellunit includes a plurality of memory cell groups. Each of the memory cellgroups includes at least one memory cell for storing data therein. Thebit line unit includes a plurality of first bit lines, each of which iscoupled to the at least one memory cell of a respective one of thememory cell groups, and a second bit line for transmitting to-be-readdata. The buffering unit includes a plurality of tri-state buffers. Eachof the tri-state buffers has an input terminal coupled to a respectiveone of the first bit lines, and an output terminal coupled to the secondbit line.

According to another aspect of this invention, a memory device comprisesa memory cell unit, a bit line unit and a buffering unit. The memorycell unit includes a plurality of memory cell groups. Each of the memorycell groups includes at least one memory cell for storing data therein.The bit line unit includes a plurality of first bit lines, each of whichis coupled to the at least one memory cell of a respective one of thememory cell groups, and a second bit line for transmitting to-be-readdata. The buffering unit includes a plurality of two-state buffers. Eachof the two-state buffers has an input terminal coupled to a respectiveone of the first bit lines, and an output terminal coupled to the secondbit line. Each of the two-state buffers is operable between an outputenable state and an output disable state based on a voltage at the inputterminal, and outputs a predetermined reference voltage at the outputterminal when operating in the output enable state.

BRIEF DESCRIPTION OF THE DRAWINGS

Other features and advantages of this invention will become apparent inthe following detailed description of the preferred embodiments of thisinvention with reference to the accompanying drawings, of which:

FIG. 1 is a schematic circuit block diagram illustrating a conventionalmemory device;

FIG. 2 is a schematic circuit block diagram illustrating the firstpreferred embodiment of a memory device according to this invention;

FIG. 3 is a schematic circuit diagram illustrating an alternative of atri-state of the first preferred embodiment;

FIG. 4 is a schematic circuit diagram illustrating an example of a firstswitch of the first preferred embodiment;

FIGS. 5 to 8 are schematic circuit block diagrams illustratingvariations of the first preferred embodiment;

FIG. 9 is a schematic circuit block diagram illustrating the secondpreferred embodiment of a memory device according to this invention;

FIG. 10 is a schematic circuit diagram illustrating an example of atwo-state buffer of the second preferred embodiment;

FIGS. 11 to 13 are schematic circuit diagrams illustrating alternativesof the two-state buffer of the second preferred embodiment; and

FIGS. 14 to 18 are schematic circuit block diagrams illustratingvariations of the second preferred embodiment.

DETAILED DESCRIPTION

Before this invention is described in greater detail with reference tothe accompanying preferred embodiments, it should be noted herein thatlike elements are denoted by the same reference numerals throughout thedisclosure.

Referring to FIG. 2, the first preferred embodiment of a memory deviceaccording to this invention includes a memory cell unit 2, a bit lineunit 3, a buffering unit 5, a plurality of first switches 52 and abiasing unit 6.

The memory cell unit 2 includes a plurality of memory cell groups 20.Each memory cell group 20 includes at least one memory cell (MC) 21 forstoring data therein. In this embodiment, the memory cell unit 2 is inthe form of a memory cell line and includes, for example, thirty-two(32) memory cell groups 20, and each memory cell group 20 includes, forexample, eight (8) memory cells 21. That is, the total number of thememory cells is, for example, two-hundred-and-fifty-six (256). However,it should be noted that the memory cell groups 20 do not necessarilyhave to have equal numbers of memory cells 21 in other embodiments ofthis invention.

The bit line unit 3 includes a plurality of first bit lines 31 eachcoupled to the memory cells 21 of a respective memory cell group 20, asecond bit line 32 for transmitting to-be-read data, a third bit line 41for transmitting to-be-written data, and a plurality of fourth bit lines42 each coupled to the memory cells 21 of a respective memory cell group20.

The buffering unit 5 includes a plurality of tri-state buffers 51. Eachtri-state buffer 51 has an input terminal coupled to a respective firstbit line 31, and an output terminal coupled to the second bit line 32.Each tri-state buffer 51 is operable between an output enable state andan output disable state, outputs one of two predetermined referencevoltages (e.g., a logic high voltage and a logic low voltage) at theoutput terminal based on a voltage at the input terminal when operatingin the output enable state, and does not output any voltage at theoutput terminal (i.e., exhibiting high impedance at the output terminal)when operating in the output disable state.

In this embodiment, each tri-state buffer 51 is a buffer that isactivated and deactivated in the output enable state and the outputdisable state, respectively. However, as shown in FIG. 3, in otherembodiments, each tri-state buffer 51 may be constituted by a buffer 515and a switch 514 that is coupled to the buffer 515 and that is turned onand off to bring the tri-state buffer 51 in the output enable state andthe output disable state, respectively.

Referring back to FIG. 2, it is noted that, for each tri-state buffer51, the voltage at the output terminal may be in-phase or anti-phasewith the voltage at the input terminal. Since each tri-state buffer 51having the anti-phase configuration may only include, for example, threetransistors, the buffering unit 5 has the advantage of occupying arelatively small area when each tri-state buffer 51 has the anti-phaseconfiguration. Moreover, if a voltage at the second bit line 32 isanti-phase with the data stored in each memory cell 21 when the memorycell 21 is read, an inverter (not shown) may be required to be coupledto the second bit line 32 for inverting the voltage at the second bitline 32.

Each first switch 52 is coupled between the third bit line 41 and arespective fourth bit line 42. In this embodiment, each first switch 52is an N-channel metal oxide semiconductor field effect transistor(MOSFET) (see FIG. 4) or alternatively, a P-channel one. However, thisinvention is not limited to such configuration. For example, each firstswitch 52 may be a field effect transistor (FET) of other types, e.g., afin field effect transistor (FinFET).

It is noted that the first switches 52 and the fourth bit lines 42 maybe omitted in other embodiments. In this case, as shown in FIG. 5, thethird bit line 41 is coupled to the memory cells 21 of each memory cellgroup 20.

Referring back to FIG. 2, the biasing unit 6 includes a plurality offirst biasing circuits (FBCs) 61 and a second biasing circuit (SBC) 62.Each first biasing circuit 61 is coupled to a respective first bit line31 and the input terminal of a respective tri-state buffer 51, andsupplies a first predetermined bias voltage thereto when none of thememory cells 21 of a respective memory cell group 20 is read. The secondbiasing circuit 62 is coupled to the second bit line 32, and supplies asecond predetermined bias voltage thereto when all of the tri-statebuffers 51 operate in the output disable state.

It is noted that each of the first and second predetermined biasvoltages may be the logic high voltage or the logic low voltage,depending on the configuration of the memory cells 21. Moreover, thesecond biasing circuit 62 may be omitted in other embodiments, in whichcase the second bit line 32 is adapted to be coupled to an externalcircuit that can supply the second predetermined bias voltage thereto.

In operation, when one of the memory cells 21 is selected to have datawritten thereinto, the corresponding first switch 52 is turned on whilethe other first switches 52 remain turned off, such that the data iswritten into the selected memory cell 21 through the third bit line 41,the corresponding first switch 52 and the corresponding fourth bit line42. When one of the memory cells 21 is selected to have data storedtherein be read, the corresponding tri-state buffer 51 switches to theoutput enable state while the other tri-state buffers 51 remain in theoutput disable state, such that the data stored in the selected memorycell 21 is read through the corresponding first bit line 31, thecorresponding tri-state buffer 51 and the second bit line 32.

It is noted that, in this embodiment, each memory cell 21 is read andwritten at different terminals. However, in other embodiments, eachmemory cell 21 may be read and written at the same terminal, in whichcase the fourth bit lines 42 are omitted, and each first switch 52 iscoupled to a respective first bit line 31 instead.

FIG. 6 illustrates a variation of the first preferred embodiment. Inthis case, the first biasing circuits 61 (see FIG. 2) are omitted, andeach memory cell group 20 further includes a dummy cell 22 that iscoupled to the respective first bit line 31. For each memory cell group20, the dummy cell 22 supplies the first predetermined bias voltage tothe respective first bit line 31 when none of the memory cells 21 isread. It is noted that the third bit line 41 (see FIG. 2), the fourthbit lines 42 (see FIG. 2) and the first switches 52 (see FIG. 2) are notdepicted in FIG. 6 for simplicity of illustration.

FIG. 7 illustrates another variation of the first preferred embodiment.In this case, the first biasing circuits 61 (see FIG. 2) are alsoomitted, and for each memory cell group 20, one of the memory cells 21serves as a parking cell (21 a), and outputs the data stored therein tobias the corresponding first bit line 31 when none of the memory cells21 is read. It is noted that the third bit line 41 (see FIG. 2), thefourth bit lines 42 (see FIG. 2) and the first switches 52 (see FIG. 2)are not depicted in FIG. 7 for simplicity of illustration.

FIG. 8 illustrates yet another variation of the first preferredembodiment. In this case, the third bit line 41 (see FIG. 2) and thefourth bit lines 42 (see FIG. 2) are omitted, and each first switch 52is coupled between a respective first bit line 31 and the second bitline 32 instead. Moreover, the second bit line 32 further transmitsto-be-written data.

In view of the above, the memory device of this embodiment shown in FIG.2 has the following advantages:

1. Since each first bit line 31 is relatively short and is coupled to arelatively small number (i.e., 8 instead of 256) of memory cells 21, acapacitance seen thereat can be reduced to 1/32 that of the conventionalmemory device (see FIG. 1). Since it is relatively easy to improvedriving capability of each tri-state buffer 51, a resistance seen at thesecond bit line 32 can be relatively small compared to the conventionalmemory device (see FIG. 1). For example, it is assumed that the memorydevice of this embodiment is fabricated using a 28 nm process. In thiscase, a time constant (e.g., 5RC) of each first bit line 31 may be 0.125ns with a resistance of 25KΩ and a capacitance of 1 fF, and a timeconstant (e.g., 5RC) of the second bit line 32 may be 0.15 ns with aresistance of 2KΩ and a capacitance of 15 fF. Due to the relativelysmall time constants, the memory device of this embodiment can be readat a relatively high frequency compared to the conventional memorydevice (see FIG. 1).

2. Since each tri-state buffer 51 assists in driving the second dataline 32, a sense amplifier is not required, thereby reducing overallpower consumption of the memory device of this embodiment.

3. By using a driving circuit (not shown) with a large drivingcapability to drive the third bit line 41, a time constant of the thirdbit line 41 can approximate that of each first bit line 31. Therefore,the memory device of this embodiment can be read and written at the sameorder of frequency.

4. Since each first biasing circuit 61 supplies the first predeterminedbias voltage to the input terminal of the respective tri-state buffer 51when none of the memory cells 21 of the respective memory cell group 20is read, the input terminal of each tri-state buffer 51 will not befloating, thereby preventing unnecessary power consumption by the memorydevice of this embodiment.

Moreover, for each of the memory devices shown respectively in FIGS. 6and 7, since the input terminal of each tri-state buffer 51 is biased bythe dummy cell 22 or the parking cell (21 a) of the respective memorycell group 20, instead of the respective first biasing circuit 61 (seeFIG. 2), the memory device has relatively low design complexity, therebyreducing design time and costs.

Referring to FIG. 9, the second preferred embodiment of a memory deviceaccording to this invention is a modification of the first preferredembodiment. Instead of the tri-state buffers 51 (see FIG. 2) of thefirst preferred embodiment, the buffering unit 5 of the second preferredembodiment includes a plurality of two-state buffers 53. Each two-statebuffer 53 has an input terminal coupled to a respective first biasingcircuit 61, and an output terminal coupled to the second bit line 32.Moreover, the memory device of the second preferred embodiment furtherincludes a plurality of second switches 7. Each second switch 7 iscoupled between the input terminal of a respective two-state buffer 53and a respective first bit line 31.

Each two-state buffer 53 is operable between an output enable state andan output disable state based on a voltage at the input terminal,outputs a predetermined reference voltage at the output terminal whenoperating in the output enable state, and does not output any voltage atthe output terminal (i.e., exhibiting high impedance at the outputterminal) when operating in the output disable state.

The predetermined reference voltage may be the logic high voltage or thelogic low voltage depending on design choice. Each two-state buffer 53may be a transistor (e.g., a FET such as a MOSFET or a FinFET) that hasa first terminal (e.g., one of a source terminal and a drain terminal)for receiving the predetermined reference voltage, a second terminal(e.g., the other of the source terminal and the drain terminal) servingas the output terminal, and a control terminal (e.g., a gate terminal)serving as the input terminal, and that is turned on and off to bringthe two-state buffer 53 in the output enable state and the outputdisable state, respectively.

In a first example, as shown in FIG. 10, the predetermined referencevoltage is the logic high voltage, and each two-state buffer 53 is anN-channel FET, such that each two-state buffer 53 outputs the logic highvoltage at the output terminal when the voltage at the input terminal issufficiently high (i.e., the two-state buffer 53 operating in the outputenable state), and exhibits high impedance at the output terminal whenthe voltage at the input terminal is sufficiently low (i.e., thetwo-state buffer 53 operating in the output disable state).

In a second example, as shown in FIG. 11, the predetermined referencevoltage is the logic low voltage, and each two-state buffer 53 is anN-channel FET, such that each two-state buffer 53 outputs the logic lowvoltage at the output terminal when the voltage at the input terminal issufficiently high (i.e., the two-state buffer 53 operating in the outputenable state), and exhibits high impedance at the output terminal whenthe voltage at the input terminal is sufficiently low (i.e., thetwo-state buffer 53 operating in the output disable state).

In a third example, as shown in FIG. 12, the predetermined referencevoltage is the logic high voltage, and each two-state buffer 53 is aP-channel FET, such that each two-state buffer 53 outputs the logic highvoltage at the output terminal when the voltage at the input terminal issufficiently low (i.e., the two-state buffer 53 operating in the outputenable state), and exhibits high impedance at the output terminal whenthe voltage at the input terminal is sufficiently high (i.e., thetwo-state buffer 53 operating in the output disable state).

In a fourth example, as shown in FIG. 13, the predetermined referencevoltage is the logic low voltage, and each two-state buffer 53 is aP-channel FET, such that each two-state buffer 53 outputs the logic lowvoltage at the output terminal when the voltage at the input terminal issufficiently low (i.e., the two-state buffer 53 operating in the outputenable state), and exhibits high impedance at the output terminal whenthe voltage at the input terminal is sufficiently high (i.e., thetwo-state buffer 53 operating in the output disable state).

Referring back to FIG. 9, each first biasing circuit 61 supplies thefirst predetermined bias voltage to the input terminal of the respectivetwo-state buffer 53 when none of the memory cells 21 of the respectivememory cell group 20 is read. The second biasing circuit 62 supplies thesecond predetermined bias voltage to the second bit line 32 when all ofthe two-state buffers 53 operate in the output disable state.

Each of the first and second predetermined bias voltages may be thelogic high voltage or the logic low voltage. When each two-state buffer53 has the configuration shown in FIG. 10, the first predetermined biasvoltage may be the logic low voltage, and the second predetermined biasvoltage may be the logic low voltage, such that each two-state buffer 53is biased to the logic low voltage at the input terminal and thusoperates in the output disable state if none of the memory cells 21 ofthe respective memory cell group 20 is read, and such that the secondbit line 32 is biased to the logic low voltage if all of the two-statebuffers 53 operate in the output disable state. In operation, one of thememory cells 21 is selected to have data stored therein be read. Whenthe data stored in the selected memory cell 21 makes the voltage at theinput terminal of the corresponding two-state buffer 53 sufficientlyhigh, the corresponding two-state buffer 53 switches to the outputenable state and outputs the logic high voltage to the second bit line32 while other two-state buffers 53 remain in the output disable state.When the data stored in the selected memory cell 21 makes the voltage atthe input terminal of the corresponding two-state buffer 53 sufficientlylow, all of the two-state buffers 53 remain in the output disable state,and the second biasing circuit 62 supplies the logic low voltage to thesecond bit line 32.

Similarly, when each two-state buffer 53 has the configuration shown inFIG. 11, the first predetermined bias voltage may be the logic lowvoltage, and the second predetermined bias voltage may be the logic highvoltage; when each two-state buffer 53 has the configuration shown inFIG. 12, the first predetermined bias voltage may be the logic highvoltage, and the second predetermined bias voltage may be the logic lowvoltage; and when each two-state buffer 53 has the configuration shownin FIG. 13, the first predetermined bias voltage may be the logic highvoltage, and the second predetermined bias voltage may be the logic highvoltage.

Referring back to FIG. 9, each second switch 7 is turned on when one ofthe memory cells 21 of the respective memory cell group 20 is read, andis turned off when none of the memory cells 21 of the respective memorycell group 20 is read. In this embodiment, each second switch 7 is anN-channel MOSFET (see FIG. 4) or may alternatively be a P-channel one.However, this invention is not limited to such configuration. Forexample, each second switch 7 may be a FET of other types, e.g., aFinFET.

It is noted that in other embodiments, the following modifications maybe made to the second preferred embodiment:

1. The second switches 7 may be omitted. In this case, the inputterminal of each two-state buffer 53 is coupled to the respective firstbit line 31.

2. The first switches 52 and the fourth bit lines 42 may be omitted. Inthis case, as shown in FIG. 14, the third bit line 41 is coupled to thememory cells 21 of each memory cell group 20.

FIG. 15 illustrates a variation of the second preferred embodiment. Inthis case, the second switches 7 (see FIG. 9) and the first biasingcircuits 61 (see FIG. 9) are omitted, the input terminal of eachtwo-state buffer 53 is coupled to the respective first bit line 31, andeach memory cell group 20 further includes a dummy cell 22 that iscoupled to the respective first bit line 31. For each memory cell group20, the dummy cell 22 supplies the first predetermined bias voltage tothe respective first bit line 31 when none of the memory cells 21 isread. It is noted that the third bit line 41 (see FIG. 9), the fourthbit lines 42 (see FIG. 9) and the first switches 52 (see FIG. 9) are notdepicted in FIG. 15 for simplicity of illustration.

FIG. 16 illustrates another variation of the second preferredembodiment. In this case, the second switches 7 (see FIG. 9) and thefirst biasing circuits 61 (see FIG. 9) are omitted, and for each memorycell group 20, one of the memory cells 21 serves as a parking cell (21a), and outputs the data stored therein to bias the corresponding firstbit line 31 when none of the memory cells 21 is read. It is noted thatthe third bit line 41 (see FIG. 9), the fourth bit lines 42 (see FIG. 9)and the first switches 52 (see FIG. 9) are not depicted in FIG. 15 forsimplicity of illustration.

FIG. 17 illustrates yet another variation of the second preferredembodiment. In this case, each second switch 7 is coupled between theoutput terminal of the respective two-state buffer 53 and the second bitline 32. For each second switch 7, when none of the memory cells 21 ofthe respective memory cell group 20 is read, the second switch 7 is off,and no current can flow through the respective two-state buffer 53 evenif the input terminal of the respective two-state buffer 53 is floating.As a result, the first biasing circuits 61 (see FIG. 9) may be omittedas shown.

FIG. 18 illustrates still another variation of the second preferredembodiment. In this case, the third bit line 41 (see FIG. 9) and thefourth bit lines 42 (see FIG. 9) are omitted, and each first switch 52is coupled between a respective first bit line 31 and the second bitline 32 instead. Moreover, the second bit line 32 further transmitsto-be-written data.

In view of the above, the memory device of this embodiment further hasthe following advantages:

1. Since the configuration of the two-state buffer 53 is simpler thanthat of the tri-state buffer 51 (see FIG. 2), and since the operatingstate of each two-state buffer 53 is controlled by the voltage at theinput terminal, the buffering unit 5 of this embodiment occupies arelatively small area, and has a relatively low design complexity and arelatively flexible layout, as compared to that of the first preferredembodiment (see FIG. 2).

2. Since all of the second switches 7 are turned off and thus thevoltage at the input terminal of each two-state buffer 53 remainsunchanged when none of the memory cells 21 is read, unnecessary powerconsumption by the memory device can be prevented even if any of thememory cells 21 outputs the data stored therein at this time.

While this invention has been described in connection with what areconsidered the most practical and preferred embodiments, it isunderstood that this invention is not limited to the disclosedembodiments but is intended to cover various arrangements includedwithin the spirit and scope of the broadest interpretation andequivalent arrangements.

What is claimed is:
 1. A memory device comprising: a memory cell unitincluding a plurality of memory cell groups, each of said memory cellgroups including at least one memory cell for storing data therein; abit line unit including a plurality of first bit lines, each of which iscoupled to said at least one memory cell of a respective one of saidmemory cell groups, and a second bit line for transmitting to-be-readdata; and a buffering unit including a plurality of two-state buffers,each of said two-state buffers having an input terminal coupled to arespective one of said first bit lines, and an output terminal coupledto said second bit line, each of said two-state buffers being operablebetween an output enable state and an output disable state based on avoltage at said input terminal, and outputting a predetermined referencevoltage at said output terminal when operating in the output enablestate.
 2. The memory device of claim 1, wherein each of said two-statebuffers is a transistor that has a first terminal for receiving thepredetermined reference voltage, a second terminal serving as saidoutput terminal, and a control terminal serving as said input terminal.3. The memory device of claim 1, wherein each of said two-state buffersis a field effect transistor that has a source terminal, a drainterminal and a gate terminal, one of said source and drain terminalsreceiving the predetermined reference voltage, the other of said sourceand drain terminals serving as said output terminal, said gate terminalserving as said input terminal.
 4. The memory device of claim 1, furthercomprising a biasing unit that is coupled to said input terminal of eachof said two-state buffers for supplying a predetermined bias voltagethereto.
 5. The memory device of claim 1, further comprising a biasingunit that is coupled to said second bit line for supplying apredetermined bias voltage thereto.
 6. The memory device of claim 1,wherein each of said memory cell groups further includes a dummy cellthat is coupled to a respective one of said first bit lines forsupplying a predetermined bias voltage thereto.
 7. The memory device ofclaim 1, wherein one of said at least one memory cell of each of saidmemory cell groups outputs the data stored therein to bias acorresponding one of said first bit lines.
 8. The memory device of claim1, further comprising a plurality of switches, each of said switchesbeing coupled between said input terminal of a respective one of saidtwo-state buffers and a respective one of said first bit lines.
 9. Thememory device of claim 1, further comprising a plurality of switches,each of said switches being coupled between said output terminal of arespective one of said two-state buffers and said second bit line. 10.The memory device of claim 1, wherein said bit line unit furtherincludes a third bit line that is coupled to said at least one memorycell of each of said memory cell groups and that transmits to-be-writtendata.
 11. The memory device of claim 1, further comprising a pluralityof switches; wherein said bit line unit further includes a third bitline for transmitting to-be-written data, and a plurality of fourth bitlines, each of which is coupled to said at least one memory cell of arespective one of said memory cell groups; and wherein each of saidswitches is coupled between said third bit line and a respective one ofsaid fourth bit lines.
 12. The memory device of claim 1, furthercomprising a plurality of switches; wherein each of said switches iscoupled between a respective one of said first bit lines and said secondbit line; and wherein said second bit line further transmitsto-be-written data.
 13. A memory device comprising: a memory cell unitincluding a plurality of memory cell groups, each of said memory cellgroups including at least one memory cell for storing data therein; abit line unit including a plurality of first bit lines, each of which iscoupled to said at least one memory cell of a respective one of saidmemory cell groups, and a second bit line for transmitting to-be-readdata; and a buffering unit including a plurality of tri-state buffers,each of said tri-state buffers having an input terminal coupled to arespective one of said first bit lines, and an output terminal coupledto said second bit line.
 14. The memory device of claim 13, furthercomprising a biasing unit that is coupled to said input terminal of eachof said tri-state buffers for supplying a predetermined bias voltagethereto.
 15. The memory device of claim 13, further comprising a biasingunit that is coupled to said second bit line for supplying apredetermined bias voltage thereto.
 16. The memory device of claim 13,wherein each of said memory cell groups further includes a dummy cellthat is coupled to the respective one of said first bit lines forsupplying a predetermined bias voltage thereto.
 17. The memory device ofclaim 13, wherein one of said at least one memory cell of each of saidmemory cell groups outputs the data stored therein to bias acorresponding one of said first bit lines.
 18. The memory device ofclaim 13, wherein said bit line unit further includes a third bit linethat is coupled to said at least one memory cell of each of said memorycell groups, and that transmits to-be-written data.
 19. The memorydevice of claim 13, further comprising a plurality of switches; whereinsaid bit line unit further includes a third bit line for transmittingto-be-written data, and a plurality of fourth bit lines, each of whichis coupled to said at least one memory cell of a respective one of saidmemory cell groups; and wherein each of said switches is coupled betweensaid third bit line and a respective one of said fourth bit lines. 20.The memory device of claim 13, further comprising a plurality ofswitches; wherein each of said switches is coupled between a respectiveone of said first bit lines and said second bit line; and wherein saidsecond bit line further transmits to-be-written data.
 21. The memorydevice of claim 13, wherein for each of said tri-state buffers, avoltage at said output terminal is anti-phase with a voltage at saidinput terminal.